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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">VPIDR_EL2, Virtualization Processor ID Register</h1><p>The VPIDR_EL2 characteristics are:</p><h2>Purpose</h2>
        <p>Holds the value of the Virtualization Processor ID. This is the value returned by EL1 reads of <a href="AArch64-midr_el1.html">MIDR_EL1</a>.</p>
      <h2>Configuration</h2><p>AArch64 System register VPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-vpidr.html">VPIDR[31:0]</a>.</p>
        <p>If EL2 is not implemented, reads of this register return the value of the <a href="AArch64-midr_el1.html">MIDR_EL1</a> and writes to the register are ignored.</p>

      
        <p>This register has no effect if EL2 is not enabled in the current Security state.</p>
      <h2>Attributes</h2>
        <p>VPIDR_EL2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="8"><a href="#fieldset_0-31_24">Implementer</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">Variant</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">Architecture</a></td><td class="lr" colspan="12"><a href="#fieldset_0-15_4">PartNum</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">Revision</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">Bits [63:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_24">Implementer, bits [31:24]</h4><div class="field">
      <p>The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:</p>
    <table class="valuetable"><tr><th>Implementer</th><th>Meaning</th></tr><tr><td class="bitfield">0x00</td><td>
          <p>Reserved for software use.</p>
        </td></tr><tr><td class="bitfield">0x41</td><td>
          <p>Arm Limited.</p>
        </td></tr><tr><td class="bitfield">0x42</td><td>
          <p>Broadcom Corporation.</p>
        </td></tr><tr><td class="bitfield">0x43</td><td>
          <p>Cavium Inc.</p>
        </td></tr><tr><td class="bitfield">0x44</td><td>
          <p>Digital Equipment Corporation.</p>
        </td></tr><tr><td class="bitfield">0x46</td><td>
          <p>Fujitsu Ltd.</p>
        </td></tr><tr><td class="bitfield">0x49</td><td>
          <p>Infineon Technologies AG.</p>
        </td></tr><tr><td class="bitfield">0x4D</td><td>
          <p>Motorola or Freescale Semiconductor Inc.</p>
        </td></tr><tr><td class="bitfield">0x4E</td><td>
          <p>NVIDIA Corporation.</p>
        </td></tr><tr><td class="bitfield">0x50</td><td>
          <p>Applied Micro Circuits Corporation.</p>
        </td></tr><tr><td class="bitfield">0x51</td><td>
          <p>Qualcomm Inc.</p>
        </td></tr><tr><td class="bitfield">0x56</td><td>
          <p>Marvell International Ltd.</p>
        </td></tr><tr><td class="bitfield">0x69</td><td>
          <p>Intel Corporation.</p>
        </td></tr><tr><td class="bitfield">0xC0</td><td>
          <p>Ampere Computing.</p>
        </td></tr></table>
      <p>Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-23_20">Variant, bits [23:20]</h4><div class="field">
      <p>An <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-19_16">Architecture, bits [19:16]</h4><div class="field">
      <p>Architecture version. Defined values are:</p>
    <table class="valuetable"><tr><th>Architecture</th><th>Meaning</th></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Armv4.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Armv4T.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>Armv5 (obsolete).</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>Armv5T.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>Armv5TE.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td>
          <p>Armv5TEJ.</p>
        </td></tr><tr><td class="bitfield">0b0111</td><td>
          <p>Armv6.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Architectural features are individually identified in the ID_* registers.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_4">PartNum, bits [15:4]</h4><div class="field"><p>An <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> primary part number for the device.</p>
<p>On processors implemented by Arm, if the top four bits of the primary part number are <span class="hexnumber">0x0</span> or <span class="hexnumber">0x7</span>, the variant and architecture are encoded differently.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_0">Revision, bits [3:0]</h4><div class="field">
      <p>An <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> revision number for the device.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing VPIDR_EL2</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, VPIDR_EL2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0000</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        X[t, 64] = NVMem[0x088];
    elsif EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    X[t, 64] = VPIDR_EL2;
elsif PSTATE.EL == EL3 then
    if !HaveEL(EL2) then
        X[t, 64] = MIDR_EL1;
    else
        X[t, 64] = VPIDR_EL2;
                </p><h4 class="assembler">MSR VPIDR_EL2, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0000</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        NVMem[0x088] = X[t, 64];
    elsif EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    VPIDR_EL2 = X[t, 64];
elsif PSTATE.EL == EL3 then
    if !HaveEL(EL2) then
        return;
    else
        VPIDR_EL2 = X[t, 64];
                </p><h4 class="assembler">MRS &lt;Xt&gt;, MIDR_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0000</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if IsFeatureImplemented(FEAT_IDST) then
        if EL2Enabled() &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGRTR_EL2.MIDR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() then
        X[t, 64] = VPIDR_EL2;
    else
        X[t, 64] = MIDR_EL1;
elsif PSTATE.EL == EL2 then
    X[t, 64] = MIDR_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = MIDR_EL1;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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